1. Field of the Invention
The invention relates to a semiconductor memory and a method of writing data into the semiconductor memory, and specifically, relates to a nonvolatile semiconductor memory that can store a plurality of data in a single memory cell, and a method for of writing such data in the nonvolatile semiconductor memory.
2. Description of the Related Art
As described in a reference (1) [patent publication JP 2002-184873A], one of the latest nonvolatile. semiconductor memory employs an SONOS (Silicon/Oxide/Nitride/Oxide/Silicon) structure. With reference to FIG. 7, a structure and an operation of a conventional nonvolatile semiconductor memory having an SONOS structure are explained as follows. FIG. 7 is a sectional view showing a skeleton framework of a single memory cell structure in a nonvolatile semiconductor memory having an SONOS structure (hereinafter called “a SONOS memory” 110).
The SONOS memory 110 includes a tunnel oxide layer 132, a capacitor layer 134 formed on the tunnel layer 132 and a top oxide layer 136 formed on the capacitor layer 134. These layers 132, 134, 136 are formed on a silicon substrate 120 in an active region defined by unillustrated isolation regions.
The SONOS memory 110 further includes a control electrode 150 formed on the top oxide layer 136. At a main surface 120a of the silicon substrate 120, first and second impurity diffusion layers 124a and 124b are formed, and the first and second impurity diffusion layers 124a and 124b sandwich an area (hereinafter called “a channel region”) at the main surface under the control gate 150. The first and second impurity diffusion layers 124a and 124b act as a source and a drain, respectively.
In the SONOS memory 110, the existence of information depends on a condition whether or not electrons are stored in the capacitor layer 134. That is, it is recognized that information is stored when electrons are stored in the capacitor layer 134. Since such a capacitor layer 134 can store electrons locally, electrons can be stored in the capacitor layer 134 in an area close to the first impurity diffusion layers 124a (e.g. drain), by generating hot carriers in an area of the channel region under the control gate close to the first impurity diffusion layers 124a. On the other hand, when hot carriers are generated in another area of the channel region under the control gate close to the second impurity diffusion layers 124b (e.g. source), electrons can be stored in the capacitor layer 134 in another area close to the source 124b. In other words, electrons can be stored in the capacitor layer 134 in either area adjacent to the drain or the source. Thus, in the SONOS memory 110, two-bit information can be stored in each single memory cell.
There is another type of a nonvolatile semiconductor memory (other than the SONOS memory 110) now available, namely a sidewall-type memory. A sidewall-type memory is disclosed in a reference (2) [patent publication JP 2005-64295A]. With reference to FIG. 8, a structure and an operation of a conventional sidewall-type memory 210 are explained as follows. FIG. 8 is a sectional view showing a skeleton framework of a single memory cell in the sidewall-type memory 210.
The sidewall-type memory 210 includes a silicon substrate 220 and a MOSFET on the substrate 220. The MOSFET includes a control gate 250, first and second impurity diffusion layers 224a and 224b, and first and second variable resistive layers 222a and 222b. The control gate is formed on a gate oxide layer 232 on an area sandwiched by the first and the second impurity diffusion layers 224a and 224b. 
The first and the second impurity diffusion layers 224a and 224b sandwich the first and the second variable resistive layers 222a and 222b, the N+ impurities are diffused therein, respectively. The first and the second impurity diffusion layers 224a and 224b act as a source and a drain of the MOSFET. In the following explanation, the first impurity diffusion layer 224a is treated as a drain, and the second impurity diffusion layer 224b is treated as a source.
Each of the first and the second variable resistive layers 222a and 222b is formed in the substrate on its main surface 220a between the one of the source and drain 224a and 224b and the area under the control gate. In both of the first and the second variable resistive layers 222a and 222b, as well as the source and drain 224a and 224b, N type impurities are diffused. The impurity concentration in each of the first and the second variable resistive layers 222a and 222b is lighter than that of the source and the drain 224a and 224b. Thus, each of the first and the second variable resistive layers 222a and 222b is defined as an N− diffusion layer while each of the source 224b and the drain 224a is defined as an N+ diffusion layer.
In the sidewall-type memory 210, a first capacitor 240a is formed on the first variable resistive layer 222a, and a second capacitor 240b is formed on the second variable resistive layer 222b. The first capacitor 240a includes a tunnel oxide layer 242a, a capacitor layer 244a formed the tunnel oxide layer 242a and the top oxide layer 246a formed on the capacitor layer 244a. The second capacitor 240b is a similar to the first capacitor 240a, that is, it includes a tunnel oxide layer 242b, a capacitor layer 244b formed the tunnel oxide layer 242b and the top oxide layer 246b formed on the capacitor layer 244b. 
In the sidewall-type memory 210, while a resistance value of the first variable resistive layer 222a is changed according to whether or not electrons are stored on the first capacitor 240a, a resistance value of the second variable resistive layer 222b is changed by according to whether or not electrons are stored on the second capacitor 240b. It is called “1” herein when electrons are stored in the first and second capacitors 240a and 240b, and “0” when electrons are not stored, in order to distinguish between the existence of data and the non-existence of data.
Injection of electrons into the first capacitor 240a is made as follows. Initially, the source 224b and the silicon substrate 110 are grounded. Then a positive voltage is applied to the control gate 250 and the drain 224a. Under this condition, the electrons that have passed through in the channel are changed to a high energy state near the drain 224a by the strong electric field toward the drain 224a. The electrons in the high energy state collide with atoms of the silicon substrate located near the electrons. As a result of the collisions, electron-hole pairs are generated. The electrons generated in this way, whose potential barrier φB is greater than that (˜3.2 eV) at the interface junction between the silicon substrate 220 and the tunnel oxide layer 242, known as “hot electrons”, are injected into the first capacitor layer 244a by an electric field toward the gate electrode 250.
To read out the information stored in the first capacitor 240a, initially, the silicon substrate 220 and the drain 224a are grounded, and then a positive voltage is applied to the control gate 250 and the source 224b. When the electrons are stored in the first capacitor 240a, the electrons stored in the first capacitor 240a induce positive charges at the first variable resistive layer 222a, which is located immediately beneath the first capacitor 240a. As a result of the inducement of positive charges, the resistance value of the first variable resistive layer 222a is increased. Thus, the electric current between the source 224b and drain 224a (channel current) is reduced. On the other hand, when the electrons are not stored in the first capacitor 240a, the resistance value of the first variable resistive layer 222a is not increased. Thus, the channel current is not reduced. Whether or not the electrons are stored is determined by the amount of the electric current. In other wards, two conditions that are the existence of data “1”, which is expressed by a small channel current flow, and the non-existence of data “0”, which is expressed by a large channel current flow, are distinguished.
As with the SONOS memory 110, it is possible to store two-bit information in each single memory cell in the sidewall-type memory 210, by switching the voltages applied between the source 224b and drain 224a. 
In recent years, the technologies have been further improved. As described above, two-bit information can be stored in each single memory cell in both the sidewall-type memory 210 and the SONOS memory 110. But, as shown in references (3) and (4) [patent publication WO 01/170/BA1 and patent publication JP 2005-116667A], new technologies, which can increase information in a single memory cell, have been introduced.
A semiconductor memory disclosed in reference (3) includes eight (8) areas where information can be stored in a single memory cell so that eight-bit information can be stored. Data for each bit is stored in the following way. Initially, two diffusion layers are selected from five diffusion layers. Then, one of the selected two layers is defined as a drain, and the other is defined as a source.
A semiconductor memory disclosed in reference (4) includes a first active area and a second active area, which intersect at a cross region with the first active area. Each of the first and second active areas includes two diffusion layers. Each of the two layers are located in one of the areas that sandwich the cross region. Therefore, the semiconductor memory disclosed in reference (4) includes four (4) areas where information can be stored in a single memory cell so that four-bit information can be stored.
However, the semiconductor memory disclosed in references (3) and (4) requires four or five-bit lines for each cell, each of which is voltage-controlled independently, so that metalized wirings may be complicated.
Furthermore, as shown in reference (5) (Non-patent publication titled “4-bit per Cell NROM Reliability”, B. Eitan et al., IEEE International Devices Meeting 2005, IEDM Technical Digest, pp. 539-542), it is proposed that data be stored in each side of one memory cell by controlling the amount of electrons injected into each side of the memory cell. According to this technology, four conditions are generated, including a first condition (A) that no electrons are injected, a second condition (B) that small amount of electrons is injected, a third condition (C) that a large amount of electrons is injected, and a fourth condition (D) that a further amount of electrons is injected. By generating the four conditions, data defined by one of four conditions can be stored in one capacitor.
FIG. 9 is a distribution chart of a threshold voltage (Vt) in a state that data is stored in one capacitor by storing electrons therein under one of the four conditions. In FIG. 9, a threshold voltage (Vt) is measured along the horizontal axis. When the threshold voltage is at VtD in a certain area of one capacitor, it is recognized that the area having the threshold voltage VtD is defined by the fourth condition (D). As well, when the threshold voltage is at one of VtC, VtB and VtA in a certain area of one capacitor, it is recognized that the area having the threshold voltage VtC, VtB or VtA is defined one of the first through third conditions (C), (B) and (A).
As described above, data defined by the four conditions can be stored in one of the first and the second capacitors. Since there are two capacitors, the first and second capacitors 240a and 240b, in the sidewall-type memory shown in FIG. 8, data defined by sixteen conditions (16=4×4), which is equal to four-bit information, can be stored without increasing bit lines according to reference (5).
However, according to the semiconductor memory disclosed in reference (5), the bottom of each distribution line is overlapped because of a production tolerance, so that it may be difficult to store data using one of four conditions in each capacitor. For this reason, it is not easy to manufacture a high reliability memory cell, and the fabrication yield goes down.